Due to pitch scaling in each generation, the spacers that define deep source/drain implants have been significantly reduced in thickness. For example, for a 22 nm node CMOS transistor the spacer thickness is less than or equal to 20 nm, whereas for 32 nm node and 45 nm node technologies, the spacer thickness is about 35 nm and about 45 nm, respectively. A small spacer thickness such as less than 20 nm makes the conventional deep source/drain implants no longer viable. This is because the lateral-implant-straggle inherent to the implant process overruns the extension for short channel devices, causing significant short channel degradation. Therefore, an in-situ doped source/drain process has attracted interest for 22 nm node and beyond CMOS transistor.
An in-situ phosphorus-doped (ISPD) embedded Si:C (eSi:C) source/drain process appears suitable for 22 nm node NMOS transistor to avoid source/drain overrunning the extension, since ISPD eSi:C offers not only doped source/drains, but also tensile channel stress. However, it was found that ISPD eSi:C has several disadvantages. For example, the ISPD eSi:C epitaxial process throughput is unacceptably low, as fewer than two wafers can be processed per hour, whereas at least four wafers per hour is considered to be an acceptable throughput. In addition, the eSi:C fill level is extremely sensitive to device pitch, and multiple pitches may be present on the same wafer. As illustrated in FIGS. 1A and 1B, respectively, for a single pitch 101 (100 nm) between gates 103, the source/drain is under-filled (fill height 105) and for a double pitch 107 (200 nm) between gates 109, the source/drain is overfilled (fill height 111). The epitaxial fill height difference causes significant variation in device parametrics, such as threshold voltage (Vt), capacitance (Cov), Ion, etc. Further, the deposition/etch-back/deposition/etch-back cyclic epitaxial process (the process during epitaxial growth wherein Si:C is periodically etched off where it is unwanted) causes extension silicon and dopant loss. Adverting to FIG. 2, spacer edge 201, with which eSi:C/Si recess boundary 203 is formed, and boundary 203 itself are eroded by the etch-back process to spacer edge 205 and boundary 207, respectively. A portion of silicon extension 209 (i.e., the portion between recess boundary 203 and boundary 207) is thus undesirably etched. This extension loss increases the resistance, is not controllable from wafer to wafer and lot to lot, and, therefore, introduces another source of variability, which is undesirable for manufacturing.
Another approach to improve the source/drain for a 22 nm node NMOS transistor is to grow N-type-doped silicon for the NMOS source/drain. Although this approach simplifies the epitaxial process, it fails to provide stress to influence channel mobility. Since the incorporation of arsenic in silicon (less than 1E20 cm-3) is low, in-situ arsenic doped silicon is not suitable as an NMOS source/drain. Although the incorporation of phosphorus in silicon (greater than 5E20 cm-3) is significantly higher than arsenic, an ISPD silicon epitaxial process for nMOS source/drains has other serious issues. For example, the ISPD silicon epitaxial throughput in NMOS transistors is relatively low, for example less than or equal to 3 wafers per hour. In addition, epitaxially deposited ISPD silicon has poor selectivity, i.e., it grows on nitride spacers, thereby causing an undesirable morphology as illustrated in FIG. 3. The ISPD silicon grows on spacers 303 and has an irregular shape. The poor morphology causes high Cov and introduces another source of device parametric variations.
A need therefore exists for methodology enabling fabrication of in-situ doped NMOS source/drains with high manufacture throughput, uniform fill level, reduced extension silicon and dopant loss, and improved morphology, and for the resulting device.